HiPC
 
 
 
 
 
 

Workshop on Embedded Systems for Media Processing
in affiliation with International Conference on
High Performance Computing Hyderabad, India

   
 
Chairs:
  S H Srinivasan , Satyam Computers
  Ravi Amur , Satyam Computers

December 17, 2003

2.00 PM – 6.00 PM

 
Highlights:

Multimedia systems represent a significant part of real-time embedded systems research. Because of the the data sizes, parallelism, signal processing aspects, and soft real-time constraints, multimedia systems are a distinguishable subset of embedded systems. The goal of the workshop is to explore hardware/software/architecture issues and applications of multimedia embedded systems.

The scope of the workshop includes but is not limited to the following topics.

  • ES Design - ASIC, hardware/software codesign

  • Media processor and system architectures - DSP, EPIC, VLIW, reconfigurable, SoC, hybrid, etc

  • Multimedia Operating Systems - kernels, scheduling, etc

  • Multimedia Languages and Compilers

  • Communication aspects - protocols, QoS, etc

  • Synchronization and integration of sensor data

  • Software architectures and User Interfaces

  • Power issues

  • Optimizations

  • Verification and validation

  • Security

  • Applications

Call for papers:

The workshop is held in conjunction with HiPC 2003. Last year's HiPC attracted around 350 international participants. Original research contributions, start of art surveys, and practices & experiences are welcome. The papers should not exceed ten single-spaced two-column pages in 10pt font.

The proceedings of the workshop will also be available electronically.

Please email your submissions (pdf, compressed postscript) to the workshop co-chairs.

IMPORTANT DATES

Participation Intention: July 15, 2003
Submission: Sep 23, 2003 (with automatic one week extension)
Notification: Oct 31, 2003
Final version due: Nov 15, 2003
Workshop: Dec 17, 2003

 

Final Program

1. Digital Watermarking in Consumer Electronics, S Adiga (Philips) Invited Speech

2. Multiprocessor Architectures for Embedded Video Streaming Applications, C P Ravikumar (Texas Instruments, India)

3. A Framework for the Design of the Heterogeneous Hierarchical Routing Architecture of a Dynamically Reconfigurable Application Specific Media Processor, Ali Akoglu, Aravind Dasu, and Sethuraman Panchanathan (Arizona State University)

4. Improving the Memory-Hierarchy Performance of Multimedia Applications, Murthy Durbhakula (Mentor Graphics India)

5. A New Technique for improving Bandwidth Utilization using Reliability Aware Path Selection, K Prabhakar (Samsung India Software Operations) and P Divyavathi (Unified Gateways Pvt Ltd)

6. Embedded System Architectures for Media Recognition, S H Srinivasan (Satyam Computer Services Ltd)